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Ambric, Inc.
15655 SW Greystone Ct.
Suite 150
Beaverton, OR 97006
Area Code 503
601-6500 Voice
601-6596 Fax
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Leading Voices
Tom R. Halfhill — Senior Analyst, In-Stat MicroProcessor Report — 11/26/2007
The Holy Grail in computer science is a high-level compiler that automatically extracts hidden parallelism from existing source code and efficiently distributes the workloads on the latest multicore processors. Ideally, programmers need not rewrite any code, and the compiler transparently targets microprocessors with any number of cores.
Dream on. Conventional serial code doesn't surrender its hidden parallelism (if, indeed, any exists) without a fight. True, a good vectorizing compiler can find some small-scale data parallelism, assuming the processor has vector-math instructions. Optimizing compilers can find some instruction-level parallelism when targeting processors with superscalar dispatching and other fancy features. And microprocessors with dynamic branch prediction, speculative execution, and out-of-order execution can find a little more parallelism at run time. But none of these techniques fully exploits the rapidly expanding resources of the latest multicore designs.
Due to those limitations, programmers must rewrite at least some of their source code to explicitly expose parallelism to the compiler or the processor. It's not the ideal solution. But for now — and possibly forever — it's the best way to keep multiple processors busy.
Shekhar Borkar, Intel Fellow, Intel Corporation, Microprocessor Technology Lab — Excerpts from an Intel paper at the 44th Design Automation Conference (DAC) special session on "Thousand-Core Chips" — 6/2007
From Multi-to-Many-Cores — Therefore, business as usual is not an option. You cannot simply follow the path of multi-core evolution, integrating multiple complex cores on a die. Instead, we propose that you integrate lots of smaller cores. Each small core delivers lower performance than a large complex core; however, the total compute throughput of the system is much higher… The many-core architecture with hundreds-to-thousands of small cores delivers unprecedented compute performance in an affordable power envelope.
During a panel session at this week's IEEE International Solid-State Circuits Conference (ISSCC) here, experts disagreed over the future limits of IC scaling. Some believe that bulk silicon still has legs. Others thought scaling was over. And some were not sure.
"When will scaling fail? It already has," said Bob Brodersen, the John Whinnery chair professor and co-scientific director of the Berkeley Wireless Research Center at the University of California at Berkeley.
Broadersen indicated that chip scaling became less important — and fell apart — during the shift towards the multi-core processor era, when power consumption and leakage was more of a concern than overall clock frequency.
Now, as the PC industry moves towards eight-core processors and beyond, the key is software, not hardware. "Parallelism is the key to the future of performance," he said. "Can the software industry meet this challenge?"
David Patterson, professor of Computer Science, University of California, Berkeley
If we can figure out how to program thousands of cores on a chip, the future looks rosy; If we can't figure it out, then things look dark.
Quotes from Ambric Press Release Introducing the Am2000 Chip Family
Robert Colwell, independent consultant, chief architect of the Intel IA32 Pentium processor, and author of the book Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chip.
I joined Ambric's technical advisory board because re-configurable computing is the right way to use extremely large-scale IC technology. It's re-configurable fabrics done right: programmability first — followed by processing granularity, memory partitioning, and then distributed interconnect paths. Ambric has banished the von Neumann memory bottleneck, long the bane of programmers trying to manually juggle multiple control threads. Power dissipation, interconnect bandwidth, complex flow control, and clock gating have been solved. They did it by simultaneously getting several great ideas right. Ambric is not just one generation ahead of other chip companies — Ambric is in another league entirely.
Berkeley Design Technology, Inc. — "Ambric Discloses Massively Parallel Architecture," InsideDSP.com — 8/23, 2006
Practical, efficient programmability is a major differentiator of Ambric's chips. The crucial importance of development ease was highlighted in the recent article "Ambric Discloses Massively Parallel Architecture," by Berkeley Design Technology, Inc. (BDTI), (InsideDSP.com, August 23, 2006). From the article:
While massively parallel processors offer the possibility of dramatic performance gains over traditional architectures, these gains will only be realized if the programming model is user friendly and efficient.
Jon Peddie, president, Jon Peddie Research, Inc.
Today's advanced video processing is leaving uni-processors in the dust. H.264 encoding for high-definition resolution is more difficult by an order-of-magnitude than is MPEG-2 at standard definition. The only way that the processing can be done in real time is to go massively parallel, and Ambric has nailed it. The chip has the brute horsepower and the ease-of-coding to handle the most difficult video processing.
Will Strauss, president of Forward Concepts
The beauty of Ambric's new chip is its programming model. Ambric has solved the chronic problem of having no practical way to program massively-parallel chips. The new Ambric chips can replace DSPs and FPGAs and deliver higher performance per dollar than either.
Gerry Kaufhold, principal analyst, In-Stat, Inc.
Video infrastructure is a hot market for high-performance re-configurable chips. Ambric's new chip is ideal for advanced applications such as video pre-processing, transcoding, rate-shaping, and other demanding algorithms. From what I've learned about the chip the image quality, compression, and throughput it produces should be world-class.
David Patterson, professor of Computer Science, University of California, Berkeley
Processors are the transistors of tomorrow.
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Enabling Rapid Time to Market for High Performance Solutions